/* the head file modifier:     g   2014-12-04 11:25:15*/

/*  
* Copyright (C) 2013 Spreadtrum Communications Inc.  
*
* This program is free software; you can redistribute it and/or  
* modify it under the terms of the GNU General Public License 
* as published by the Free Software Foundation; either version 2 
* of the License, or (at your option) any later version.  
* 
* This program is distributed in the hope that it will be useful, 
* but WITHOUT ANY WARRANTY; without even the implied warranty of 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
* GNU General Public License for more details.  
* 
*************************************************  
* Automatically generated C header: do not edit *  
*************************************************  
*/  
#ifndef __H_REGS_ANA_HEADFILE_H__
#define __H_REGS_ANA_HEADFILE_H__ __FILE__

/* registers definitions for ANA_APB */
#define REG_ANA_APB_RST_CTRL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0000)/*RST_CTRL*/
#define REG_ANA_APB_PWR_CTRL0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0004)/*PWR_CTRL0*/
#define REG_ANA_APB_PWR_CTRL1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0008)/*PWR_CTRL1*/
#define REG_ANA_APB_REC_XTAL_CFG			SCI_ADDR(REGS_ANA_APB_BASE, 0x000C)/*REC_XTAL_CFG*/
#define REG_ANA_APB_BB_BG_CTRL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0010)/*BB_BG_CTRL*/
#define REG_ANA_APB_M_AAPC_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x0014)/*M_AAPC_CFG*/
#define REG_ANA_APB_S_AAPC_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x0018)/*S_AAPC_CFG*/
#define REG_ANA_APB_RTC4M_0_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x001C)/*RTC4M_0_CFG*/
#define REG_ANA_APB_RTC100M_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x0020)/*RTC100M_CFG*/
#define REG_ANA_APB_MPLL0_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0024)/*MPLL0_CFG0*/
#define REG_ANA_APB_MPLL0_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0028)/*MPLL0_CFG1*/
#define REG_ANA_APB_MPLL1_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x002C)/*MPLL1_CFG0*/
#define REG_ANA_APB_MPLL1_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0030)/*MPLL1_CFG1*/
#define REG_ANA_APB_DPLL0_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0034)/*DPLL0_CFG0*/
#define REG_ANA_APB_DPLL0_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0038)/*DPLL0_CFG1*/
#define REG_ANA_APB_DPLL1_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x003C)/*DPLL1_CFG0*/
#define REG_ANA_APB_DPLL1_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0040)/*DPLL1_CFG1*/
#define REG_ANA_APB_RPLL0_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0044)/*RPLL0_CFG0*/
#define REG_ANA_APB_RPLL0_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0048)/*RPLL0_CFG1*/
#define REG_ANA_APB_RPLL0_CFG2				SCI_ADDR(REGS_ANA_APB_BASE, 0x004C)/*RPLL0_CFG2*/
#define REG_ANA_APB_RPLL1_CFG0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0050)/*RPLL1_CFG0*/
#define REG_ANA_APB_RPLL1_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0054)/*RPLL1_CFG1*/
#define REG_ANA_APB_RPLL1_CFG2				SCI_ADDR(REGS_ANA_APB_BASE, 0x0058)/*RPLL1_CFG2*/
#define REG_ANA_APB_TWPLL_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x005C)/*TWPLL_CFG1*/
#define REG_ANA_APB_TWPLL_CFG2				SCI_ADDR(REGS_ANA_APB_BASE, 0x0060)/*TWPLL_CFG2*/
#define REG_ANA_APB_LTEPLL_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0064)/*LTEPLL_CFG1*/
#define REG_ANA_APB_LTEPLL_CFG2				SCI_ADDR(REGS_ANA_APB_BASE, 0x0068)/*LTEPLL_CFG2*/
#define REG_ANA_APB_LTECAPLL_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x006C)/*LTECAPLL_CFG1*/
#define REG_ANA_APB_LTECAPLL_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x0070)/*LTECAPLL_CFG2*/
#define REG_ANA_APB_M_LVDSRF_PLL_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0074)/*M_LVDSRF_PLL_CFG1*/
#define REG_ANA_APB_M_LVDSRF_PLL_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x0078)/*M_LVDSRF_PLL_CFG2*/
#define REG_ANA_APB_M_LVDSRF_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x007C)/*M_LVDSRF_CFG1*/
#define REG_ANA_APB_M_LVDSRF_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x0080)/*M_LVDSRF_CFG2*/
#define REG_ANA_APB_M_LVDSRF_CFG3			SCI_ADDR(REGS_ANA_APB_BASE, 0x0084)/*M_LVDSRF_CFG3*/
#define REG_ANA_APB_S_LVDSRF_PLL_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0088)/*S_LVDSRF_PLL_CFG1*/
#define REG_ANA_APB_S_LVDSRF_PLL_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x008C)/*S_LVDSRF_PLL_CFG2*/
#define REG_ANA_APB_S_LVDSRF_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0090)/*S_LVDSRF_CFG1*/
#define REG_ANA_APB_S_LVDSRF_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x0094)/*S_LVDSRF_CFG2*/
#define REG_ANA_APB_S_LVDSRF_CFG3			SCI_ADDR(REGS_ANA_APB_BASE, 0x0098)/*S_LVDSRF_CFG3*/
#define REG_ANA_APB_GPLL_CFG1				SCI_ADDR(REGS_ANA_APB_BASE, 0x009C)/*GPLL_CFG1*/
#define REG_ANA_APB_GPLL_CFG2				SCI_ADDR(REGS_ANA_APB_BASE, 0x00A0)/*GPLL_CFG2*/
#define REG_ANA_APB_LVDSDISPLL_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00A4)/*LVDSDISPLL_CFG1*/
#define REG_ANA_APB_LVDSDISPLL_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00A8)/*LVDSDISPLL_CFG2*/
#define REG_ANA_APB_LVDSDIS_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x00AC)/*LVDSDIS_CFG*/
#define REG_ANA_APB_THM0_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x00B0)/*THM0_CFG*/
#define REG_ANA_APB_THM1_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x00B4)/*THM1_CFG*/
#define REG_ANA_APB_THM2_CFG				SCI_ADDR(REGS_ANA_APB_BASE, 0x00B8)/*THM2_CFG*/
#define REG_ANA_APB_GPU_VDROP SNSR_CTRL			SCI_ADDR(REGS_ANA_APB_BASE, 0x00BC)/*GPU_VDROP SNSR_CTRL*/
#define REG_ANA_APB_A53_CORE_VDROP SNSR_CTRL		SCI_ADDR(REGS_ANA_APB_BASE, 0x00C0)/*A53_CORE_VDROP SNSR_CTRL*/
#define REG_ANA_APB_USB20_PHY_TUNE			SCI_ADDR(REGS_ANA_APB_BASE, 0x00C4)/*USB20_PHY_TUNE*/
#define REG_ANA_APB_USB20_PHY_TEST			SCI_ADDR(REGS_ANA_APB_BASE, 0x00C8)/*USB20_PHY_TEST*/
#define REG_ANA_APB_USB20_PHY_CTRL1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00CC)/*USB20_PHY_CTRL1*/
#define REG_ANA_APB_USB20_PHY_CTRL2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00D0)/*USB20_PHY_CTRL2*/
#define REG_ANA_APB_HSIC_PHY_TUNE			SCI_ADDR(REGS_ANA_APB_BASE, 0x00D4)/*HSIC_PHY_TUNE*/
#define REG_ANA_APB_HSIC_PHY_TEST			SCI_ADDR(REGS_ANA_APB_BASE, 0x00D8)/*HSIC_PHY_TEST*/
#define REG_ANA_APB_HSIC_PHY_CTRL1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00DC)/*HSIC_PHY_CTRL1*/
#define REG_ANA_APB_HSIC_PHY_CTRL2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00E0)/*HSIC_PHY_CTRL2*/
#define REG_ANA_APB_USB30_PHY_TUNE1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00E4)/*USB30_PHY_TUNE1*/
#define REG_ANA_APB_USB30_PHY_TUNE2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00E8)/*USB30_PHY_TUNE2*/
#define REG_ANA_APB_USB30_PHY_TEST			SCI_ADDR(REGS_ANA_APB_BASE, 0x00EC)/*USB30_PHY_TEST*/
#define REG_ANA_APB_USB30_PHY_CTRL1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00F0)/*USB30_PHY_CTRL1*/
#define REG_ANA_APB_USB30_PHY_CTRL2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00F4)/*USB30_PHY_CTRL2*/
#define REG_ANA_APB_USB30_PHY_DBG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x00F8)/*USB30_PHY_DBG1*/
#define REG_ANA_APB_USB30_PHY_DBG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x00FC)/*USB30_PHY_DBG2*/
#define REG_ANA_APB_MIPI_PHY_CTRL1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0100)/*MIPI_PHY_CTRL1*/
#define REG_ANA_APB_MIPI_PHY_CTRL2			SCI_ADDR(REGS_ANA_APB_BASE, 0x0104)/*MIPI_PHY_CTRL2*/
#define REG_ANA_APB_MIPI_PHY_CTRL3			SCI_ADDR(REGS_ANA_APB_BASE, 0x0108)/*MIPI_PHY_CTRL3*/
#define REG_ANA_APB_MIPI_PHY_CTRL4			SCI_ADDR(REGS_ANA_APB_BASE, 0x010C)/*MIPI_PHY_CTRL4*/
#define REG_ANA_APB_MPLL_CAL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0110)/*MPLL_CAL*/
#define REG_ANA_APB_RPLL_CAL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0114)/*RPLL_CAL*/
#define REG_ANA_APB_DPLL_CAL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0118)/*DPLL_CAL*/
#define REG_ANA_APB_TWPLL_CAL				SCI_ADDR(REGS_ANA_APB_BASE, 0x011C)/*TWPLL_CAL*/
#define REG_ANA_APB_LPLL_CAL				SCI_ADDR(REGS_ANA_APB_BASE, 0x0120)/*LPLL_CAL*/
#define REG_ANA_APB_LVDS_PLL_CAL			SCI_ADDR(REGS_ANA_APB_BASE, 0x0124)/*LVDS_PLL_CAL*/
#define REG_ANA_APB_DISP_PLL_CAL			SCI_ADDR(REGS_ANA_APB_BASE, 0x0128)/*DISP_PLL_CAL*/
#define REG_ANA_APB_PLL_FREQ_CAL_CFG			SCI_ADDR(REGS_ANA_APB_BASE, 0x012C)/*PLL_FREQ_CAL_CFG*/
#define REG_ANA_APB_MPLL_RESULT				SCI_ADDR(REGS_ANA_APB_BASE, 0x0130)/*MPLL_RESULT*/
#define REG_ANA_APB_RPLL_RESULT				SCI_ADDR(REGS_ANA_APB_BASE, 0x0134)/*RPLL_RESULT*/
#define REG_ANA_APB_DPLL_RESULT				SCI_ADDR(REGS_ANA_APB_BASE, 0x0138)/*DPLL_RESULT*/
#define REG_ANA_APB_TWPLL_RESULT			SCI_ADDR(REGS_ANA_APB_BASE, 0x013C)/*TWPLL_RESULT*/
#define REG_ANA_APB_LPLL_RESULT				SCI_ADDR(REGS_ANA_APB_BASE, 0x0140)/*LPLL_RESULT*/
#define REG_ANA_APB_LVDS_PLL_RESULT			SCI_ADDR(REGS_ANA_APB_BASE, 0x0144)/*LVDS_PLL_RESULT*/
#define REG_ANA_APB_DISP_PLL_RESULT			SCI_ADDR(REGS_ANA_APB_BASE, 0x0148)/*DISP_PLL_RESULT*/
#define REG_ANA_APB_PLL_TEST_FLAG			SCI_ADDR(REGS_ANA_APB_BASE, 0x014C)/*PLL_TEST_FLAG*/
#define REG_ANA_APB_MIPI_TEST				SCI_ADDR(REGS_ANA_APB_BASE, 0x0150)/*l*/
#define REG_ANA_APB_MIPI_TEST2				SCI_ADDR(REGS_ANA_APB_BASE, 0x0154)/*MIPI_TEST2*/
#define REG_ANA_APB_MIPI_CSI0_RESERVE			SCI_ADDR(REGS_ANA_APB_BASE, 0x0158)/*MIPI_CSI0_RESERVE*/
#define REG_ANA_APB_MIPI_CSI1_RESERVE			SCI_ADDR(REGS_ANA_APB_BASE, 0x015C)/*MIPI_CSI1_RESERVE*/
#define REG_ANA_APB_MIPI_DSI0_RESERVE			SCI_ADDR(REGS_ANA_APB_BASE, 0x0160)/*MIPI_DSI0_RESERVE*/
#define REG_ANA_APB_MIPI_DSI1_RESERVE			SCI_ADDR(REGS_ANA_APB_BASE, 0x0164)/*MIPI_DSI1_RESERVE*/
#define REG_ANA_APB_LVDSDISP_BIST_CFG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0168)/*LVDSDISP_BIST_CFG1*/
#define REG_ANA_APB_LVDSDISP_BIST_CFG2			SCI_ADDR(REGS_ANA_APB_BASE, 0x016C)/*LVDSDISP_BIST_CFG2*/
#define REG_ANA_APB_LVDSDISP_BIST_CFG3			SCI_ADDR(REGS_ANA_APB_BASE, 0x0170)/*LVDSDISP_BIST_CFG3*/
#define REG_ANA_APB_MACRO_POWER_FLAG0			SCI_ADDR(REGS_ANA_APB_BASE, 0x0174)/*MACRO_POWER_FLAG0*/
#define REG_ANA_APB_MACRO_POWER_FLAG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0178)/*MACRO_POWER_FLAG1*/
#define REG_ANA_APB_MACRO_RESET_FLAG0			SCI_ADDR(REGS_ANA_APB_BASE, 0x017C)/*MACRO_RESET_FLAG0*/
#define REG_ANA_APB_MACRO_CHECK_FLAG0			SCI_ADDR(REGS_ANA_APB_BASE, 0x0180)/*MACRO_CHECK_FLAG0*/
#define REG_ANA_APB_MACRO_CHECK_FLAG1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0184)/*MACRO_CHECK_FLAG1*/
#define REG_ANA_APB_PLL_CLKOUT_AUTO_GATE0		SCI_ADDR(REGS_ANA_APB_BASE, 0x0188)/*PLL_CLKOUT_AUTO_GATE0*/
#define REG_ANA_APB_PLL_CLKOUT_AUTO_GATE1		SCI_ADDR(REGS_ANA_APB_BASE, 0x018C)/*PLL_CLKOUT_AUTO_GATE1*/
#define REG_ANA_APB_AGLB_SEL0				SCI_ADDR(REGS_ANA_APB_BASE, 0x0200)/*AGLB_SEL0*/
#define REG_ANA_APB_AGLB_SEL1				SCI_ADDR(REGS_ANA_APB_BASE, 0x0204)/*AGLB_SEL1*/
#define REG_ANA_APB_SW_TEST				SCI_ADDR(REGS_ANA_APB_BASE, 0x0404)/*SW_TEST*/
#define REG_ANA_APB_ANLG_RESERVED1			SCI_ADDR(REGS_ANA_APB_BASE, 0x0408)/*ANLG_RESERVED1*/
#define REG_ANA_APB_ANLG_RESERVED2			SCI_ADDR(REGS_ANA_APB_BASE, 0x040C)/*ANLG_RESERVED2*/



/* bits definitions for register REG_ANA_APB_RST_CTRL */
#define BIT_ANA_APB_HSIC_PHY_SOFT_RST				(BIT(2))
#define BIT_ANA_APB_USB30_PHY_SOFT_RST				(BIT(1))
#define BIT_ANA_APB_USB20_PHY_SOFT_RST				(BIT(0))

/* bits definitions for register REG_ANA_APB_PWR_CTRL0 */
#define BIT_ANA_APB_LVDSDISPLL_PD				(BIT(18))
#define BIT_ANA_APB_GPLL_PD					(BIT(17))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_PD				(BIT(16))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_PD				(BIT(15))
#define BIT_ANA_APB_LPLL1_PD					(BIT(14))
#define BIT_ANA_APB_LPLL0_PD					(BIT(13))
#define BIT_ANA_APB_TWPLL_PD					(BIT(12))
#define BIT_ANA_APB_RPLL1_PD					(BIT(11))
#define BIT_ANA_APB_RPLL0_PD					(BIT(10))
#define BIT_ANA_APB_DPLL1_PD					(BIT(9))
#define BIT_ANA_APB_DPLL0_PD					(BIT(8))
#define BIT_ANA_APB_MPLL1_PD					(BIT(7))
#define BIT_ANA_APB_MPLL0_PD					(BIT(6))
#define BIT_ANA_APB_S_AAPC_PD					(BIT(5))
#define BIT_ANA_APB_M_AAPC_PD					(BIT(4))
#define BIT_ANA_APB_BB_BG_PD					(BIT(3))
#define BIT_ANA_APB_REC_32MHZ_1_BUF_PD				(BIT(2))
#define BIT_ANA_APB_REC_32MHZ_0_BUF_PD				(BIT(1))
#define BIT_ANA_APB_REC_26MHZ_0_BUF_PD				(BIT(0))

/* bits definitions for register REG_ANA_APB_PWR_CTRL1 */
#define BIT_ANA_APB_USB30_PS_PD					(BIT(18))
#define BIT_ANA_APB_USB20_PHY_PD				(BIT(17))
#define BIT_ANA_APB_HSIC_PD_PHY					(BIT(16))
#define BIT_ANA_APB_USB20_PS_PD_S				(BIT(15))
#define BIT_ANA_APB_USB20_PS_PD_L				(BIT(14))
#define BIT_ANA_APB_HSIC_PS_PD_S				(BIT(13))
#define BIT_ANA_APB_HSIC_PS_PD_L				(BIT(12))
#define BIT_ANA_APB_FORCE_DSI_PHY_SHUTDOWNZ_S			(BIT(11))
#define BIT_ANA_APB_FORCE_DSI_PHY_SHUTDOWNZ_M			(BIT(10))
#define BIT_ANA_APB_FORCE_CSI0_PHY_SHUTDOWNZ			(BIT(9))
#define BIT_ANA_APB_FORCE_CSI1_PHY_SHUTDOWNZ			(BIT(8))
#define BIT_ANA_APB_MIPI_DSI_PS_PD_S_S				(BIT(7))
#define BIT_ANA_APB_MIPI_DSI_PS_PD_L_S				(BIT(6))
#define BIT_ANA_APB_MIPI_DSI_PS_PD_S_M				(BIT(5))
#define BIT_ANA_APB_MIPI_DSI_PS_PD_L_M				(BIT(4))
#define BIT_ANA_APB_MIPI_CSI0_PS_PD_S				(BIT(3))
#define BIT_ANA_APB_MIPI_CSI0_PS_PD_L				(BIT(2))
#define BIT_ANA_APB_MIPI_CSI1_PS_PD_S				(BIT(1))
#define BIT_ANA_APB_MIPI_CSI1_PS_PD_L				(BIT(0))

/* bits definitions for register REG_ANA_APB_REC_XTAL_CFG */
#define BIT_ANA_APB_ANALOG_PLL_RESERVE(_X_)			((_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_ANALOG_TESTMUX(_X_)			((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_PROBE_SEL(_X_)				((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))
#define BIT_ANA_APB_SINDRV_ENA_SQUARE				(BIT(7))
#define BIT_ANA_APB_SINDRV_ENA					(BIT(6))
#define BIT_ANA_APB_REC_32MHZ_1_CUR_SEL				(BIT(2))
#define BIT_ANA_APB_REC_32MHZ_0_CUR_SEL				(BIT(1))
#define BIT_ANA_APB_REC_26MHZ_0_CUR_SEL				(BIT(0))

/* bits definitions for register REG_ANA_APB_BB_BG_CTRL */
#define BIT_ANA_APB_ANA_BB_RESERVE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_BB_CON_BG					(BIT(2))
#define BIT_ANA_APB_BB_BG_RBIAS_EN				(BIT(1))
#define BIT_ANA_APB_BB_BG_IEXT_IBEN				(BIT(0))

/* bits definitions for register REG_ANA_APB_M_AAPC_CFG */
#define BIT_ANA_APB_AAPC_G2(_X_)				((_X_) << 26 & (BIT(26)|BIT(27)))
#define BIT_ANA_APB_AAPC_G1(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)))
#define BIT_ANA_APB_AAPC_G0(_X_)				((_X_) << 22 & (BIT(22)|BIT(23)))
#define BIT_ANA_APB_M_AAPC_SEL					(BIT(21))
#define BIT_ANA_APB_M_AAPC_BPRES				(BIT(20))
#define BIT_ANA_APB_M_AAPC_RESERVE(_X_)			((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_M_APCOUT_SEL(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_M_AAPC_LOW_V_CON				(BIT(15))
#define BIT_ANA_APB_M_AAPC_D(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))

/* bits definitions for register REG_ANA_APB_S_AAPC_CFG */
#define BIT_ANA_APB_S_AAPC_SEL					(BIT(21))
#define BIT_ANA_APB_S_AAPC_BPRES				(BIT(20))
#define BIT_ANA_APB_S_AAPC_RESERVE(_X_)			((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_S_APCOUT_SEL(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_S_AAPC_LOW_V_CON				(BIT(15))
#define BIT_ANA_APB_S_AAPC_D(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))

/* bits definitions for register REG_ANA_APB_RTC4M_0_CFG */
#define BIT_ANA_APB_RTC4M0_RSTB					(BIT(23))
#define BIT_ANA_APB_RTC4M0_EN					(BIT(22))
#define BIT_ANA_APB_RTC4M0_RC_C(_X_)				((_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_RTC4M0_RESERVE(_X_)			((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)))
#define BIT_ANA_APB_RTC4M0_I_C(_X_)				((_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)))
#define BIT_ANA_APB_RTC4M0_CHOP_EN				(BIT(0))

/* bits definitions for register REG_ANA_APB_RTC100M_CFG */
#define BIT_ANA_APB_RTC100M_RSTB				(BIT(23))
#define BIT_ANA_APB_RTC100M_EN					(BIT(22))
#define BIT_ANA_APB_RTC100M_RC_C(_X_)				((_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_RTC100M_RESERVE(_X_)			((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)))
#define BIT_ANA_APB_RTC100M_I_C(_X_)				((_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)))
#define BIT_ANA_APB_RTC100M_CHOP_EN				(BIT(0))

/* bits definitions for register REG_ANA_APB_MPLL0_CFG0 */
#define BIT_ANA_APB_MPLL0_RESERVE(_X_)				((_X_) << 29 & (BIT(29)|BIT(30)))
#define BIT_ANA_APB_MPLL0_LOCK_DONE				(BIT(28))
#define BIT_ANA_APB_MPLL0_DIV_S					(BIT(27))
#define BIT_ANA_APB_MPLL0_MOD_EN				(BIT(26))
#define BIT_ANA_APB_MPLL0_SDM_EN				(BIT(25))
#define BIT_ANA_APB_MPLL0_REF_SEL(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)))
#define BIT_ANA_APB_MPLL0_LPF(_X_)				((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_MPLL0_REFIN(_X_)				((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_MPLL0_IBIAS(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_MPLL0_RST					(BIT(14))
#define BIT_ANA_APB_MPLL0_CLKOUT_EN				(BIT(13))
#define BIT_ANA_APB_MPLL0_DIV32_EN				(BIT(12))
#define BIT_ANA_APB_MPLL0_FRELESS1G				(BIT(11))
#define BIT_ANA_APB_MPLL0_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_MPLL0_CFG1 */
#define BIT_ANA_APB_MPLL0_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_MPLL0_PD_SEL				(BIT(20))
#define BIT_ANA_APB_MPLL0_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_MPLL1_CFG0 */
#define BIT_ANA_APB_MPLL1_RESERVE(_X_)				((_X_) << 29 & (BIT(29)|BIT(30)))
#define BIT_ANA_APB_MPLL1_LOCK_DONE				(BIT(28))
#define BIT_ANA_APB_MPLL1_DIV_S					(BIT(27))
#define BIT_ANA_APB_MPLL1_MOD_EN				(BIT(26))
#define BIT_ANA_APB_MPLL1_SDM_EN				(BIT(25))
#define BIT_ANA_APB_MPLL1_REF_SEL(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)))
#define BIT_ANA_APB_MPLL1_LPF(_X_)				((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_MPLL1_REFIN(_X_)				((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_MPLL1_IBIAS(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_MPLL1_RST					(BIT(14))
#define BIT_ANA_APB_MPLL1_CLKOUT_EN				(BIT(13))
#define BIT_ANA_APB_MPLL1_DIV32_EN				(BIT(12))
#define BIT_ANA_APB_MPLL1_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_MPLL1_CFG1 */
#define BIT_ANA_APB_MPLL1_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_MPLL1_PD_SEL				(BIT(20))
#define BIT_ANA_APB_MPLL1_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_DPLL0_CFG0 */
#define BIT_ANA_APB_DPLL0_RESERVE(_X_)				((_X_) << 29 & (BIT(29)|BIT(30)))
#define BIT_ANA_APB_DPLL0_LOCK_DONE				(BIT(28))
#define BIT_ANA_APB_DPLL0_DIV_S					(BIT(27))
#define BIT_ANA_APB_DPLL0_MOD_EN				(BIT(26))
#define BIT_ANA_APB_DPLL0_SDM_EN				(BIT(25))
#define BIT_ANA_APB_DPLL0_LPF(_X_)				((_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)))
#define BIT_ANA_APB_DPLL0_REFIN(_X_)				((_X_) << 20 & (BIT(20)|BIT(21)))
#define BIT_ANA_APB_DPLL0_IBIAS(_X_)				((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_DPLL0_CLKOUT_EN				(BIT(17))
#define BIT_ANA_APB_DPLL0_DIV1_EN				(BIT(16))
#define BIT_ANA_APB_DPLL0_DIV2_EN				(BIT(15))
#define BIT_ANA_APB_DPLL0_DIV3_EN				(BIT(14))
#define BIT_ANA_APB_DPLL0_DIV4_EN				(BIT(13))
#define BIT_ANA_APB_DPLL0_DIV5_EN				(BIT(12))
#define BIT_ANA_APB_DPLL0_DIV7_EN				(BIT(11))
#define BIT_ANA_APB_DPLL0_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_DPLL0_CFG1 */
#define BIT_ANA_APB_DPLL0_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_DPLL0_REF_SEL				(BIT(23))
#define BIT_ANA_APB_DPLL0_PD_SEL				(BIT(22))
#define BIT_ANA_APB_DPLL0_RST					(BIT(20))
#define BIT_ANA_APB_DPLL0_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_DPLL1_CFG0 */
#define BIT_ANA_APB_DPLL1_RESERVE(_X_)				((_X_) << 30 & (BIT(30)|BIT(31)))
#define BIT_ANA_APB_DPLL1_LOCK_DONE				(BIT(29))
#define BIT_ANA_APB_DPLL1_REF_SEL(_X_)				((_X_) << 27 & (BIT(27)|BIT(28)))
#define BIT_ANA_APB_DPLL1_DIV_S					(BIT(26))
#define BIT_ANA_APB_DPLL1_MOD_EN				(BIT(25))
#define BIT_ANA_APB_DPLL1_SDM_EN				(BIT(24))
#define BIT_ANA_APB_DPLL1_LPF(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_DPLL1_REFIN(_X_)				((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_DPLL1_IBIAS(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_DPLL1_DIV1_EN				(BIT(16))
#define BIT_ANA_APB_DPLL1_DIV2_EN				(BIT(15))
#define BIT_ANA_APB_DPLL1_DIV3_EN				(BIT(14))
#define BIT_ANA_APB_DPLL1_DIV4_EN				(BIT(13))
#define BIT_ANA_APB_DPLL1_DIV5_EN				(BIT(12))
#define BIT_ANA_APB_DPLL1_DIV7_EN				(BIT(11))
#define BIT_ANA_APB_DPLL1_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_DPLL1_CFG1 */
#define BIT_ANA_APB_DPLL1_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_DPLL1_CLKOUT_EN				(BIT(23))
#define BIT_ANA_APB_DPLL1_PD_SEL				(BIT(22))
#define BIT_ANA_APB_DPLL1_RST					(BIT(20))
#define BIT_ANA_APB_DPLL1_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_RPLL0_CFG0 */
#define BIT_ANA_APB_RPLL0_PD_SEL				(BIT(30))
#define BIT_ANA_APB_RPLL0_RST					(BIT(28))
#define BIT_ANA_APB_RPLL0_N(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)))
#define BIT_ANA_APB_RPLL0_IBIAS(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)))
#define BIT_ANA_APB_RPLL0_LPF(_X_)				((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_RPLL0_REFIN(_X_)				((_X_) << 10 & (BIT(10)|BIT(11)))
#define BIT_ANA_APB_RPLL0_NINT(_X_)				((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_RPLL0_DIV_S					(BIT(3))
#define BIT_ANA_APB_RPLL0_REF_SEL(_X_)				((_X_) << 1 & (BIT(1)|BIT(2)))
#define BIT_ANA_APB_RPLL0_LOCK_DONE				(BIT(0))

/* bits definitions for register REG_ANA_APB_RPLL0_CFG1 */
#define BIT_ANA_APB_RPLL0_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)))

/* bits definitions for register REG_ANA_APB_RPLL0_CFG2 */
#define BIT_ANA_APB_RPLL0_DIV1_EN				(BIT(18))
#define BIT_ANA_APB_RPLL0_SDM_EN				(BIT(17))
#define BIT_ANA_APB_RPLL0_MOD_EN				(BIT(16))
#define BIT_ANA_APB_RPLL0_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_RPLL1_CFG0 */
#define BIT_ANA_APB_RPLL1_PD_SEL				(BIT(30))
#define BIT_ANA_APB_RPLL1_RST					(BIT(28))
#define BIT_ANA_APB_RPLL1_N(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)))
#define BIT_ANA_APB_RPLL1_IBIAS(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)))
#define BIT_ANA_APB_RPLL1_LPF(_X_)				((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_RPLL1_REFIN(_X_)				((_X_) << 10 & (BIT(10)|BIT(11)))
#define BIT_ANA_APB_RPLL1_NINT(_X_)				((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_RPLL1_DIV_S					(BIT(3))
#define BIT_ANA_APB_RPLL1_REF_SEL(_X_)				((_X_) << 1 & (BIT(1)|BIT(2)))
#define BIT_ANA_APB_RPLL1_LOCK_DONE				(BIT(0))

/* bits definitions for register REG_ANA_APB_RPLL1_CFG1 */
#define BIT_ANA_APB_RPLL1_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)))

/* bits definitions for register REG_ANA_APB_RPLL1_CFG2 */
#define BIT_ANA_APB_RPLL1_DIV1_EN				(BIT(18))
#define BIT_ANA_APB_RPLL1_SDM_EN				(BIT(17))
#define BIT_ANA_APB_RPLL1_MOD_EN				(BIT(16))
#define BIT_ANA_APB_RPLL1_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_TWPLL_CFG1 */
#define BIT_ANA_APB_TWPLL_RESERVE(_X_)				((_X_) << 30 & (BIT(30)|BIT(31)))
#define BIT_ANA_APB_TWPLL_LOCK_DONE				(BIT(29))
#define BIT_ANA_APB_TWPLL_DIV_S					(BIT(26))
#define BIT_ANA_APB_TWPLL_MOD_EN				(BIT(25))
#define BIT_ANA_APB_TWPLL_SDM_EN				(BIT(24))
#define BIT_ANA_APB_TWPLL_LPF(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_TWPLL_REFIN(_X_)				((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_TWPLL_IBIAS(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_TWPLL_CLKOUT_EN				(BIT(16))
#define BIT_ANA_APB_TWPLL_DIV1_EN				(BIT(15))
#define BIT_ANA_APB_TWPLL_DIV2_EN				(BIT(14))
#define BIT_ANA_APB_TWPLL_DIV3_EN				(BIT(13))
#define BIT_ANA_APB_TWPLL_DIV5_EN				(BIT(12))
#define BIT_ANA_APB_TWPLL_DIV7_EN				(BIT(11))
#define BIT_ANA_APB_TWPLL_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_TWPLL_CFG2 */
#define BIT_ANA_APB_TWPLL_REF_SEL(_X_)				((_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_TWPLL_NINT(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)))
#define BIT_ANA_APB_TWPLL_PD_SEL				(BIT(22))
#define BIT_ANA_APB_TWPLL_RST					(BIT(20))
#define BIT_ANA_APB_TWPLL_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_LTEPLL_CFG1 */
#define BIT_ANA_APB_LPLL0_DIV3_EN				(BIT(31))
#define BIT_ANA_APB_LPLL0_LOCK_DONE				(BIT(30))
#define BIT_ANA_APB_LPLL0_REF_SEL(_X_)				((_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LPLL0_DIV_S					(BIT(26))
#define BIT_ANA_APB_LPLL0_MOD_EN				(BIT(25))
#define BIT_ANA_APB_LPLL0_SDM_EN				(BIT(24))
#define BIT_ANA_APB_LPLL0_LPF(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_LPLL0_REFIN(_X_)				((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_LPLL0_IBIAS(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_LPLL0_RESERVED(_X_)			((_X_) << 15 & (BIT(15)|BIT(16)))
#define BIT_ANA_APB_LPLL0_CLKOUT_EN				(BIT(14))
#define BIT_ANA_APB_LPLL0_DIV1_EN				(BIT(13))
#define BIT_ANA_APB_LPLL0_DIV2_EN				(BIT(12))
#define BIT_ANA_APB_LPLL0_DIV5_EN				(BIT(11))
#define BIT_ANA_APB_LPLL0_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_LTEPLL_CFG2 */
#define BIT_ANA_APB_LPLL0_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LPLL0_PD_SEL				(BIT(22))
#define BIT_ANA_APB_LPLL0_RST					(BIT(20))
#define BIT_ANA_APB_LPLL0_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_LTECAPLL_CFG1 */
#define BIT_ANA_APB_LPLL1_DIV3_EN				(BIT(31))
#define BIT_ANA_APB_LPLL1_LOCK_DONE				(BIT(30))
#define BIT_ANA_APB_LPLL1_REF_SEL(_X_)				((_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LPLL1_DIV_S					(BIT(26))
#define BIT_ANA_APB_LPLL1_MOD_EN				(BIT(25))
#define BIT_ANA_APB_LPLL1_SDM_EN				(BIT(24))
#define BIT_ANA_APB_LPLL1_LPF(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_LPLL1_REFIN(_X_)				((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_LPLL1_IBIAS(_X_)				((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_LPLL1_RESERVED(_X_)			((_X_) << 15 & (BIT(15)|BIT(16)))
#define BIT_ANA_APB_LPLL1_CLKOUT_EN				(BIT(14))
#define BIT_ANA_APB_LPLL1_DIV1_EN				(BIT(13))
#define BIT_ANA_APB_LPLL1_DIV2_EN				(BIT(12))
#define BIT_ANA_APB_LPLL1_DIV5_EN				(BIT(11))
#define BIT_ANA_APB_LPLL1_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_LTECAPLL_CFG2 */
#define BIT_ANA_APB_LPLL1_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LPLL1_PD_SEL				(BIT(22))
#define BIT_ANA_APB_LPLL1_RST					(BIT(20))
#define BIT_ANA_APB_LPLL1_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_M_LVDSRF_PLL_CFG1 */
#define BIT_ANA_APB_M_LVDSRF_LVPLL_REFIN(_X_)			((_X_) << 30 & (BIT(30)|BIT(31)))
#define BIT_ANA_APB_M_LVDSRF_NINT(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_REFCK_SEL(_X_)		((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_M_LVDSRF_PLL_CLKOUT_EN			(BIT(19))
#define BIT_ANA_APB_M_LVDSRF_PLL_DIVOUT_EN			(BIT(18))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_RST				(BIT(16))
#define BIT_ANA_APB_M_LVDSRF_SDM_EN				(BIT(15))
#define BIT_ANA_APB_M_LVDSRF_MOD_EN				(BIT(14))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_DIV_S			(BIT(13))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_IBIAS(_X_)			((_X_) << 11 & (BIT(11)|BIT(12)))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_N(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_M_LVDSRF_PLL_CFG2 */
#define BIT_ANA_APB_M_LVDSRF_LOCKDONE				(BIT(31))
#define BIT_ANA_APB_M_LVDSRF_LVPLL_LPF(_X_)			((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_M_LVDSRF_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)))

/* bits definitions for register REG_ANA_APB_M_LVDSRF_CFG1 */
#define BIT_ANA_APB_M_LVDSRF_TXIMP(_X_)			((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_M_LVDSRF_SER_RST				(BIT(27))
#define BIT_ANA_APB_M_LVDSRF_RXIMP_CAL(_X_)			((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)))
#define BIT_ANA_APB_M_LVDSRF_RXIMP_CAL_EN			(BIT(23))
#define BIT_ANA_APB_M_LVDSRF_RXIMP(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_M_LVDSRF_LOWSPEED_MODE			(BIT(18))
#define BIT_ANA_APB_M_LVDSRF_EQ(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_M_LVDSRF_IO12				(BIT(15))
#define BIT_ANA_APB_M_LVDSRF_CUR2X_EN				(BIT(13))
#define BIT_ANA_APB_M_LVDSRF_POSTDIV(_X_)			((_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)))

/* bits definitions for register REG_ANA_APB_M_LVDSRF_CFG2 */
#define BIT_ANA_APB_M_LVDSRF_OFF_OCT				(BIT(27))
#define BIT_ANA_APB_M_LVDSRF_RESERVE(_X_)			((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)))
#define BIT_ANA_APB_M_LVDSRF_RXCOM(_X_)			((_X_) << 21 & (BIT(21)|BIT(22)))
#define BIT_ANA_APB_M_LVDSRF_TXCOM(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_M_LVDSRF_DES_RST1				(BIT(18))
#define BIT_ANA_APB_M_LVDSRF_DES_RST0				(BIT(17))
#define BIT_ANA_APB_M_LVDSRF_RXPD1				(BIT(16))
#define BIT_ANA_APB_M_LVDSRF_RXPD0				(BIT(15))
#define BIT_ANA_APB_M_LVDSRF_PHASE1(_X_)			((_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_M_LVDSRF_PHASE0(_X_)			((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_M_LVDSRF_TXSW(_X_)				((_X_) << 3 & (BIT(3)|BIT(4)))
#define BIT_ANA_APB_M_LVDSRF_TXPD				(BIT(2))
#define BIT_ANA_APB_M_LVDSRF_RXBIAS_TRIM(_X_)			((_X_) & (BIT(0)|BIT(1)))

/* bits definitions for register REG_ANA_APB_M_LVDSRF_CFG3 */
#define BIT_ANA_APB_M_LVDSRF_RXRESERVED(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_M_LVDSRF_TXRESERVED(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_S_LVDSRF_PLL_CFG1 */
#define BIT_ANA_APB_S_LVDSRF_LVPLL_REFIN(_X_)			((_X_) << 30 & (BIT(30)|BIT(31)))
#define BIT_ANA_APB_S_LVDSRF_NINT(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_REFCK_SEL(_X_)		((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_S_LVDSRF_PLL_CLKOUT_EN			(BIT(19))
#define BIT_ANA_APB_S_LVDSRF_PLL_DIVOUT_EN			(BIT(18))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_RST				(BIT(16))
#define BIT_ANA_APB_S_LVDSRF_SDM_EN				(BIT(15))
#define BIT_ANA_APB_S_LVDSRF_MOD_EN				(BIT(14))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_DIV_S			(BIT(13))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_IBIAS(_X_)			((_X_) << 11 & (BIT(11)|BIT(12)))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_N(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_S_LVDSRF_PLL_CFG2 */
#define BIT_ANA_APB_S_LVDSRF_LOCKDONE				(BIT(31))
#define BIT_ANA_APB_S_LVDSRF_LVPLL_LPF(_X_)			((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_S_LVDSRF_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)))

/* bits definitions for register REG_ANA_APB_S_LVDSRF_CFG1 */
#define BIT_ANA_APB_S_LVDSRF_TXIMP(_X_)			((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_S_LVDSRF_SER_RST				(BIT(27))
#define BIT_ANA_APB_S_LVDSRF_RXIMP_CAL(_X_)			((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)))
#define BIT_ANA_APB_S_LVDSRF_RXIMP_CAL_EN			(BIT(23))
#define BIT_ANA_APB_S_LVDSRF_RXIMP(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_S_LVDSRF_LOWSPEED_MODE			(BIT(18))
#define BIT_ANA_APB_S_LVDSRF_EQ(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_S_LVDSRF_IO12				(BIT(15))
#define BIT_ANA_APB_S_LVDSRF_CUR2X_EN				(BIT(13))
#define BIT_ANA_APB_S_LVDSRF_POSTDIV(_X_)			((_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)))

/* bits definitions for register REG_ANA_APB_S_LVDSRF_CFG2 */
#define BIT_ANA_APB_S_LVDSRF_OFF_OCT				(BIT(27))
#define BIT_ANA_APB_S_LVDSRF_RESERVE(_X_)			((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)))
#define BIT_ANA_APB_S_LVDSRF_RXCOM(_X_)			((_X_) << 21 & (BIT(21)|BIT(22)))
#define BIT_ANA_APB_S_LVDSRF_TXCOM(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_S_LVDSRF_DES_RST1				(BIT(18))
#define BIT_ANA_APB_S_LVDSRF_DES_RST0				(BIT(17))
#define BIT_ANA_APB_S_LVDSRF_RXPD1				(BIT(16))
#define BIT_ANA_APB_S_LVDSRF_RXPD0				(BIT(15))
#define BIT_ANA_APB_S_LVDSRF_PHASE1(_X_)			((_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_S_LVDSRF_PHASE0(_X_)			((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_S_LVDSRF_TXSW(_X_)				((_X_) << 3 & (BIT(3)|BIT(4)))
#define BIT_ANA_APB_S_LVDSRF_TXPD				(BIT(2))
#define BIT_ANA_APB_S_LVDSRF_RXBIAS_TRIM(_X_)			((_X_) & (BIT(0)|BIT(1)))

/* bits definitions for register REG_ANA_APB_S_LVDSRF_CFG3 */
#define BIT_ANA_APB_S_LVDSRF_RXRESERVED(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_S_LVDSRF_TXRESERVED(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_GPLL_CFG1 */
#define BIT_ANA_APB_GPLL_RESERVE(_X_)				((_X_) << 25 & (BIT(25)|BIT(26)))
#define BIT_ANA_APB_GPLL_LOCK_DONE				(BIT(24))
#define BIT_ANA_APB_GPLL_REF_SEL(_X_)				((_X_) << 22 & (BIT(22)|BIT(23)))
#define BIT_ANA_APB_GPLL_DIV_S					(BIT(21))
#define BIT_ANA_APB_GPLL_MOD_EN					(BIT(20))
#define BIT_ANA_APB_GPLL_SDM_EN					(BIT(19))
#define BIT_ANA_APB_GPLL_LPF(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)))
#define BIT_ANA_APB_GPLL_REFIN(_X_)				((_X_) << 14 & (BIT(14)|BIT(15)))
#define BIT_ANA_APB_GPLL_IBIAS(_X_)				((_X_) << 12 & (BIT(12)|BIT(13)))
#define BIT_ANA_APB_GPLL_CLKOUT_EN				(BIT(11))
#define BIT_ANA_APB_GPLL_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_GPLL_CFG2 */
#define BIT_ANA_APB_GPLL_NINT(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_GPLL_PD_SEL					(BIT(22))
#define BIT_ANA_APB_GPLL_RST					(BIT(20))
#define BIT_ANA_APB_GPLL_KINT(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_LVDSDISPLL_CFG1 */
#define BIT_ANA_APB_LVDSDISPLL_LOCK_DONE			(BIT(27))
#define BIT_ANA_APB_LVDSDISPLL_DIV_S				(BIT(26))
#define BIT_ANA_APB_LVDSDISPLL_MOD_EN				(BIT(25))
#define BIT_ANA_APB_LVDSDISPLL_SDM_EN				(BIT(24))
#define BIT_ANA_APB_LVDSDISPLL_LPF(_X_)			((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_LVDSDISPLL_REFIN(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_LVDSDISPLL_IBIAS(_X_)			((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_LVDSDIS_PLL_REFCK_SEL			(BIT(16))
#define BIT_ANA_APB_LVDSDISPLL_PD_SEL				(BIT(15))
#define BIT_ANA_APB_LVDSDIS_PLL_RST				(BIT(13))
#define BIT_ANA_APB_LVDSDIS_PLL_CLKOUT_EN			(BIT(12))
#define BIT_ANA_APB_LVDSDIS_PLL_DIVOUT_EN			(BIT(11))
#define BIT_ANA_APB_LVDSDISPLL_N(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))

/* bits definitions for register REG_ANA_APB_LVDSDISPLL_CFG2 */
#define BIT_ANA_APB_LVDSDISPLL_REF_SEL				(BIT(30))
#define BIT_ANA_APB_LVDSDISPLL_NINT(_X_)			((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LVDSDIS_PLL_POSTDIV(_X_)			((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_LVDSDISPLL_KINT(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))

/* bits definitions for register REG_ANA_APB_LVDSDIS_CFG */
#define BIT_ANA_APB_LVDSDIS_SER_RSTN				(BIT(24))
#define BIT_ANA_APB_LVDSDIS_TXIMP(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_LVDSDIS_TXPD(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)))
#define BIT_ANA_APB_LVDSDIS_OFF_CL				(BIT(14))
#define BIT_ANA_APB_LVDSDIS_TXCOM(_X_)				((_X_) << 12 & (BIT(12)|BIT(13)))
#define BIT_ANA_APB_LVDSDIS_TXSLEW(_X_)			((_X_) << 10 & (BIT(10)|BIT(11)))
#define BIT_ANA_APB_LVDSDIS_TXSW(_X_)				((_X_) << 8 & (BIT(8)|BIT(9)))
#define BIT_ANA_APB_LVDSDIS_TXRESERVE(_X_)			((_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)))
#define BIT_ANA_APB_LVDSDIS_PRE_EMP(_X_)			((_X_) << 1 & (BIT(1)|BIT(2)))
#define BIT_ANA_APB_LVDSDIS_OFF_OCT				(BIT(0))

/* bits definitions for register REG_ANA_APB_THM0_CFG */
#define BIT_ANA_APB_THM0_CALI_RSVD(_X_)			((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_THM0_RST					(BIT(13))
#define BIT_ANA_APB_THM0_PD					(BIT(12))
#define BIT_ANA_APB_THM0_VBE_SEL				(BIT(11))
#define BIT_ANA_APB_THM0_VREF_CHOPEN				(BIT(10))
#define BIT_ANA_APB_THM0_CHOP_EN				(BIT(9))
#define BIT_ANA_APB_THM0_RESERVE(_X_)				((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)))
#define BIT_ANA_APB_THM0_BJT_SEL(_X_)				((_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)))
#define BIT_ANA_APB_THM0_TEST(_X_)				((_X_) & (BIT(0)|BIT(1)))

/* bits definitions for register REG_ANA_APB_THM1_CFG */
#define BIT_ANA_APB_THM1_RST					(BIT(13))
#define BIT_ANA_APB_THM1_PD					(BIT(12))
#define BIT_ANA_APB_THM1_VBE_SEL				(BIT(11))
#define BIT_ANA_APB_THM1_VREF_CHOPEN				(BIT(10))
#define BIT_ANA_APB_THM1_CHOP_EN				(BIT(9))
#define BIT_ANA_APB_THM1_RESERVE(_X_)				((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)))
#define BIT_ANA_APB_THM1_BJT_SEL(_X_)				((_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)))
#define BIT_ANA_APB_THM1_TEST(_X_)				((_X_) & (BIT(0)|BIT(1)))

/* bits definitions for register REG_ANA_APB_THM2_CFG */
#define BIT_ANA_APB_THM2_CALI_RSVD(_X_)			((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_THM2_RST					(BIT(13))
#define BIT_ANA_APB_THM2_PD					(BIT(12))
#define BIT_ANA_APB_THM2_VBE_SEL				(BIT(11))
#define BIT_ANA_APB_THM2_VREF_CHOPEN				(BIT(10))
#define BIT_ANA_APB_THM2_CHOP_EN				(BIT(9))
#define BIT_ANA_APB_THM2_RESERVE(_X_)				((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)))
#define BIT_ANA_APB_THM2_BJT_SEL(_X_)				((_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)))
#define BIT_ANA_APB_THM2_TEST(_X_)				((_X_) & (BIT(0)|BIT(1)))

/* bits definitions for register REG_ANA_APB_GPU_VDROP SNSR_CTRL */
#define BIT_ANA_APB_GPU_VDROP1_RESERVED_CTRL(_X_)		((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)))
#define BIT_ANA_APB_GPU_VDROP1_CTRL(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_GPU_VDROP1_CURRENT_CTRL(_X_)		((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_GPU_VDROP1_EN				(BIT(16))
#define BIT_ANA_APB_GPU_VDROP1_OUT				(BIT(10))
#define BIT_ANA_APB_GPU_VDROP0_OUT				(BIT(9))
#define BIT_ANA_APB_GPU_VDROP0_RESERVED_CTRL(_X_)		((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)))
#define BIT_ANA_APB_GPU_VDROP0_CTRL(_X_)			((_X_) << 3 & (BIT(3)|BIT(4)))
#define BIT_ANA_APB_GPU_VDROP0_CURRENT_CTRL(_X_)		((_X_) << 1 & (BIT(1)|BIT(2)))
#define BIT_ANA_APB_GPU_VDROP0_EN				(BIT(0))

/* bits definitions for register REG_ANA_APB_A53_CORE_VDROP SNSR_CTRL */
#define BIT_ANA_APB_CA53_BIG_VDROP0_OUT				(BIT(25))
#define BIT_ANA_APB_CA53_BIG_VDROP0_RESERVED_CTRL(_X_)		((_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)))
#define BIT_ANA_APB_CA53_BIG_VDROP0_CTRL(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)))
#define BIT_ANA_APB_CA53_BIG_VDROP0_CURRENT_CTRL(_X_)		((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_CA53_BIG_VDROP0_EN				(BIT(16))
#define BIT_ANA_APB_CA53_LIT_VDROP0_OUT				(BIT(9))
#define BIT_ANA_APB_CA53_LIT_VDROP0_RESERVED_CTRL(_X_)		((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)))
#define BIT_ANA_APB_CA53_LIT_VDROP0_CTRL(_X_)			((_X_) << 3 & (BIT(3)|BIT(4)))
#define BIT_ANA_APB_CA53_LIT_VDROP0_CURRENT_CTRL(_X_)		((_X_) << 1 & (BIT(1)|BIT(2)))
#define BIT_ANA_APB_CA53_LIT_VDROP0_EN				(BIT(0))

/* bits definitions for register REG_ANA_APB_USB20_PHY_TUNE */
#define BIT_ANA_APB_USB20_TUNEEQ(_X_)				((_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)))
#define BIT_ANA_APB_USB20_TUNEDSC(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)))
#define BIT_ANA_APB_USB20_TUNEOTG(_X_)				((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_USB20_TUNEHSAMP(_X_)			((_X_) << 18 & (BIT(18)|BIT(19)))
#define BIT_ANA_APB_USB20_TUNEPLLS(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)))
#define BIT_ANA_APB_USB20_TF12KRES(_X_)			((_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
#define BIT_ANA_APB_USB20_TFHSRES(_X_)				((_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_USB20_TUNERISE(_X_)			((_X_) << 3 & (BIT(3)|BIT(4)))
#define BIT_ANA_APB_USB20_TUNESQ(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)))

/* bits definitions for register REG_ANA_APB_USB20_PHY_TEST */
#define BIT_ANA_APB_USB20_VBUSVLDEXTSEL				(BIT(26))
#define BIT_ANA_APB_USB20_VBUSVLDEXT				(BIT(25))
#define BIT_ANA_APB_USB20_OTGDISABLE				(BIT(24))
#define BIT_ANA_APB_USB20_T2RCOMP				(BIT(21))
#define BIT_ANA_APB_USB20_BIST_T2R				(BIT(20))
#define BIT_ANA_APB_USB20_LPBK_END				(BIT(19))
#define BIT_ANA_APB_USB20_LPBK					(BIT(18))
#define BIT_ANA_APB_USB20_TESTDATAOUT(_X_)			((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)))
#define BIT_ANA_APB_USB20_TESTCLK				(BIT(13))
#define BIT_ANA_APB_USB20_TESTDATAOUTSEL			(BIT(12))
#define BIT_ANA_APB_USB20_TESTADDR(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
#define BIT_ANA_APB_USB20_TESTDATAIN(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))

/* bits definitions for register REG_ANA_APB_USB20_PHY_CTRL1 */
#define BIT_ANA_APB_USB20_XCVRSELECT(_X_)			((_X_) << 28 & (BIT(28)|BIT(29)))
#define BIT_ANA_APB_USB20_DATABUS16_8				(BIT(27))
#define BIT_ANA_APB_USB20_TERMSELECT				(BIT(26))
#define BIT_ANA_APB_USB20_OPMODE(_X_)				((_X_) << 24 & (BIT(24)|BIT(25)))
#define BIT_ANA_APB_USB20_BYPASS_DRV_DP				(BIT(23))
#define BIT_ANA_APB_USB20_BYPASS_DRV_DM				(BIT(22))
#define BIT_ANA_APB_USB20_RESERVE(_X_)				((_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_USB20_REXTENABLE				(BIT(5))
#define BIT_ANA_APB_USB20_TXBITTUFFENABLEH			(BIT(4))
#define BIT_ANA_APB_USB20_TXBITTUFFENABLE			(BIT(3))
#define BIT_ANA_APB_USB20_DMPULLUP				(BIT(2))
#define BIT_ANA_APB_USB20_S_ID					(BIT(1))
#define BIT_ANA_APB_HSIC_PLLON					(BIT(0))

/* bits definitions for register REG_ANA_APB_USB20_PHY_CTRL2 */
#define BIT_ANA_APB_USB20_BYPASS_IN_DM				(BIT(9))
#define BIT_ANA_APB_USB20_BYPASS_IN_DP				(BIT(8))
#define BIT_ANA_APB_USB20_BYPASS_FS				(BIT(7))
#define BIT_ANA_APB_USB20_TXVALIDH				(BIT(6))
#define BIT_ANA_APB_USB20_TXVALID				(BIT(5))
#define BIT_ANA_APB_USB20_DMPULLDOWN				(BIT(4))
#define BIT_ANA_APB_USB20_DPPULLDOWN				(BIT(3))
#define BIT_ANA_APB_USB20_SUSPENDM				(BIT(2))
#define BIT_ANA_APB_USB20_RESET					(BIT(1))
#define BIT_ANA_APB_USB20_PORN					(BIT(0))

/* bits definitions for register REG_ANA_APB_HSIC_PHY_TUNE */
#define BIT_ANA_APB_HSIC_TXRPUTUNE(_X_)			((_X_) << 6 & (BIT(6)|BIT(7)))
#define BIT_ANA_APB_HSIC_TXRPDTUNE(_X_)			((_X_) << 4 & (BIT(4)|BIT(5)))
#define BIT_ANA_APB_HSIC_TXSRTUNE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))

/* bits definitions for register REG_ANA_APB_HSIC_PHY_TEST */
#define BIT_ANA_APB_HSIC_SIDDQ					(BIT(21))
#define BIT_ANA_APB_HSIC_BISTERROR				(BIT(20))
#define BIT_ANA_APB_HSIC_BISTDONE				(BIT(19))
#define BIT_ANA_APB_HSIC_LOOPBACKENB				(BIT(18))
#define BIT_ANA_APB_HSIC_TESTDATAOUT(_X_)			((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)))
#define BIT_ANA_APB_HSIC_TESTCLK				(BIT(13))
#define BIT_ANA_APB_HSIC_TESTDATAOUTSEL				(BIT(12))
#define BIT_ANA_APB_HSIC_TESTADDR(_X_)				((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
#define BIT_ANA_APB_HSIC_TESTDATAIN(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))

/* bits definitions for register REG_ANA_APB_HSIC_PHY_CTRL1 */
#define BIT_ANA_APB_HSIC_PORTRESET				(BIT(12))
#define BIT_ANA_APB_HSIC_POR					(BIT(11))
#define BIT_ANA_APB_HSIC_SUSPENDM				(BIT(10))
#define BIT_ANA_APB_HSIC_XCVRSELECT				(BIT(9))
#define BIT_ANA_APB_HSIC_WORDINTERFACE				(BIT(8))
#define BIT_ANA_APB_HSIC_TXVALIDH				(BIT(7))
#define BIT_ANA_APB_HSIC_TXVALID				(BIT(6))
#define BIT_ANA_APB_HSIC_OPMODE(_X_)				((_X_) << 4 & (BIT(4)|BIT(5)))
#define BIT_ANA_APB_HSIC_DMPULLDOWN				(BIT(3))
#define BIT_ANA_APB_HSIC_DPPULLDOWN				(BIT(2))
#define BIT_ANA_APB_HSIC_TXBITTUFFENH				(BIT(1))
#define BIT_ANA_APB_HSIC_TXBITTUFFEN				(BIT(0))

/* bits definitions for register REG_ANA_APB_HSIC_PHY_CTRL2 */
#define BIT_ANA_APB_HSIC_RESERVE(_X_)				(_X_)

/* bits definitions for register REG_ANA_APB_USB30_PHY_TUNE1 */
#define BIT_ANA_APB_USB30_COMPDISTUNE0(_X_)			((_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_USB30_OTGTUNE0(_X_)			((_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)))
#define BIT_ANA_APB_USB30_SQRXTUNE0(_X_)			((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)))
#define BIT_ANA_APB_USB30_TXFSLSTUNE0(_X_)			((_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_USB30_TXHSXVTUNE0(_X_)			((_X_) << 17 & (BIT(17)|BIT(18)))
#define BIT_ANA_APB_USB30_TXPREEMPAMPTUNE0(_X_)		((_X_) << 15 & (BIT(15)|BIT(16)))
#define BIT_ANA_APB_USB30_TXPREEMPPULSETUNE0			(BIT(14))
#define BIT_ANA_APB_USB30_TXRESTUNE0(_X_)			((_X_) << 12 & (BIT(12)|BIT(13)))
#define BIT_ANA_APB_USB30_TXRISETUNE0(_X_)			((_X_) << 10 & (BIT(10)|BIT(11)))
#define BIT_ANA_APB_USB30_TXVREFTUNE0(_X_)			((_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)))
#define BIT_ANA_APB_USB30_LOS_BIAS(_X_)			((_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)))
#define BIT_ANA_APB_USB30_TX_VBOOST_LVL(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)))

/* bits definitions for register REG_ANA_APB_USB30_PHY_TUNE2 */
#define BIT_ANA_APB_USB30_RTUNE_ACK				(BIT(30))
#define BIT_ANA_APB_USB30_PCS_RX_LOS_MASK_VAL(_X_)		((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_USB30_PCS_TX_DEEMPH_3P5DB(_X_)		((_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)))
#define BIT_ANA_APB_USB30_PCS_TX_DEEMPH_6DB(_X_)		((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))
#define BIT_ANA_APB_USB30_PCS_TX_SWING_FULL(_X_)		((_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
#define BIT_ANA_APB_USB30_RTUNE_REQ				(BIT(0))

/* bits definitions for register REG_ANA_APB_USB30_PHY_TEST */
#define BIT_ANA_APB_USB30_IDDIG0_CFG_SEL			(BIT(21))
#define BIT_ANA_APB_USB30_IDDIG0_REG				(BIT(20))
#define BIT_ANA_APB_USB30_VBUSVALID0_CFG_SEL			(BIT(19))
#define BIT_ANA_APB_USB30_VBUSVALID0_REG			(BIT(18))
#define BIT_ANA_APB_USB30_BVALID0_CFG_SEL			(BIT(17))
#define BIT_ANA_APB_USB30_BVALID0_REG				(BIT(16))
#define BIT_ANA_APB_USB30_PIPEP_POWERPRESENT_CFG_SEL		(BIT(15))
#define BIT_ANA_APB_USB30_PIPEP_POWERPRESENT_REG		(BIT(14))
#define BIT_ANA_APB_USB30_JTAG_TRST_N				(BIT(13))
#define BIT_ANA_APB_USB30_JTAG_TDI				(BIT(12))
#define BIT_ANA_APB_USB30_JTAG_TDO				(BIT(11))
#define BIT_ANA_APB_USB30_JTAG_TDO_EN				(BIT(10))
#define BIT_ANA_APB_USB30_JTAG_TMS				(BIT(9))
#define BIT_ANA_APB_USB30_JTAG_TCK				(BIT(8))
#define BIT_ANA_APB_USB30_PIPEP_POWERDOWN(_X_)			((_X_) << 6 & (BIT(6)|BIT(7)))
#define BIT_ANA_APB_USB30_ATERESET				(BIT(4))
#define BIT_ANA_APB_USB30_LOOPBACKENB0				(BIT(3))
#define BIT_ANA_APB_USB30_TEST_POWERDOWN_HSP			(BIT(2))
#define BIT_ANA_APB_USB30_TEST_POWERDOWN_SSP			(BIT(1))
#define BIT_ANA_APB_USB30_VATESTENB				(BIT(0))

/* bits definitions for register REG_ANA_APB_USB30_PHY_CTRL1 */
#define BIT_ANA_APB_USB30_PORTRESET0				(BIT(29))
#define BIT_ANA_APB_USB30_FSEL(_X_)				((_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)))
#define BIT_ANA_APB_USB30_MPLL_MULTIPLIER(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_USB30_REF_CLKDIV2				(BIT(15))
#define BIT_ANA_APB_USB30_REF_SSP_EN				(BIT(14))
#define BIT_ANA_APB_USB30_REF_USE_PAD				(BIT(13))
#define BIT_ANA_APB_USB30_SSC_EN				(BIT(12))
#define BIT_ANA_APB_USB30_SSC_RANGE(_X_)			((_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)))
#define BIT_ANA_APB_USB30_SSC_REF_CLK_SEL(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)))

/* bits definitions for register REG_ANA_APB_USB30_PHY_CTRL2 */
#define BIT_ANA_APB_USB30_PIPEP_TX_ONES_ZEROS			(BIT(27))
#define BIT_ANA_APB_USB30_PIPEP_TX_ELECIDLE			(BIT(26))
#define BIT_ANA_APB_USB30_PIPEP_TX_DETECTRX			(BIT(25))
#define BIT_ANA_APB_USB30_PIPEP_TX_DEEMPH(_X_)			((_X_) << 23 & (BIT(23)|BIT(24)))
#define BIT_ANA_APB_USB30_PIPEP_RX_TERMINATION			(BIT(22))
#define BIT_ANA_APB_USB30_PIPEP_RX_POLARITY			(BIT(21))
#define BIT_ANA_APB_USB30_PIPEP_RX_EQ_TRAINING			(BIT(20))
#define BIT_ANA_APB_USB30_PIPEP_ELASTICITY_BUF_MODE		(BIT(19))
#define BIT_ANA_APB_USB30_DRVVBUS0				(BIT(18))
#define BIT_ANA_APB_USB30_IDPULLUP0				(BIT(17))
#define BIT_ANA_APB_USB30_PHY_RESET				(BIT(16))
#define BIT_ANA_APB_USB30_TXVALIDH				(BIT(15))
#define BIT_ANA_APB_USB30_TXVALID				(BIT(14))
#define BIT_ANA_APB_USB30_ACJT_LEVEL(_X_)			((_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))
#define BIT_ANA_APB_USB30_COMMONONN				(BIT(8))
#define BIT_ANA_APB_USB30_PIPEP_RESET_N				(BIT(7))
#define BIT_ANA_APB_USB30_OTGDISABLE0				(BIT(6))
#define BIT_ANA_APB_USB30_VBUSVLDEXTSEL0			(BIT(5))
#define BIT_ANA_APB_USB30_VBUSVLDEXT0				(BIT(4))
#define BIT_ANA_APB_USB30_ALT_CLK_EN				(BIT(3))
#define BIT_ANA_APB_USB30_ALT_CLK_SEL				(BIT(2))
#define BIT_ANA_APB_USB30_LANE0_EXT_PCLK_REQ			(BIT(1))
#define BIT_ANA_APB_USB30_LANE0_TX2RX_LOOPBK			(BIT(0))

/* bits definitions for register REG_ANA_APB_USB30_PHY_DBG1 */
#define BIT_ANA_APB_USB30_XCVRSEL0(_X_)			((_X_) << 29 & (BIT(29)|BIT(30)))
#define BIT_ANA_APB_USB30_WORDINTERFACE0			(BIT(28))
#define BIT_ANA_APB_USB30_TXBITTUFFENH0			(BIT(27))
#define BIT_ANA_APB_USB30_TXBITTUFFEN0				(BIT(26))
#define BIT_ANA_APB_USB30_TERMSEL0				(BIT(25))
#define BIT_ANA_APB_USB30_SUSPENDM0				(BIT(24))
#define BIT_ANA_APB_USB30_SLEEPM0				(BIT(23))
#define BIT_ANA_APB_USB30_OPMODE0(_X_)				((_X_) << 21 & (BIT(21)|BIT(22)))
#define BIT_ANA_APB_USB30_DPPULLDOWN0				(BIT(20))
#define BIT_ANA_APB_USB30_DMPULLDOWN0				(BIT(19))
#define BIT_ANA_APB_USB30_TXENABLEN0				(BIT(18))
#define BIT_ANA_APB_USB30_FSXCVROWNER0				(BIT(17))
#define BIT_ANA_APB_USB30_FSSE0EXT0				(BIT(16))
#define BIT_ANA_APB_USB30_FSDATAEXT0				(BIT(15))
#define BIT_ANA_APB_USB30_BYPASSSEL0				(BIT(14))
#define BIT_ANA_APB_USB30_BYPASSDMEN0				(BIT(13))
#define BIT_ANA_APB_USB30_BYPASSDPEN0				(BIT(12))
#define BIT_ANA_APB_USB30_BYPASSDMDATA0				(BIT(11))
#define BIT_ANA_APB_USB30_BYPASSDPDATA0				(BIT(10))
#define BIT_ANA_APB_USB30_VDATSRCENB0				(BIT(9))
#define BIT_ANA_APB_USB30_VDATDETENB0				(BIT(8))
#define BIT_ANA_APB_USB30_CHRGSEL0				(BIT(7))
#define BIT_ANA_APB_USB30_DCDENB0				(BIT(6))
#define BIT_ANA_APB_USB30_HSXCVREXTCTL0				(BIT(5))
#define BIT_ANA_APB_USB30_CR_ACK				(BIT(4))
#define BIT_ANA_APB_USB30_CR_CAP_ADDR				(BIT(3))
#define BIT_ANA_APB_USB30_CR_CAP_DATA				(BIT(2))
#define BIT_ANA_APB_USB30_CR_READ				(BIT(1))
#define BIT_ANA_APB_USB30_CR_WRITE				(BIT(0))

/* bits definitions for register REG_ANA_APB_USB30_PHY_DBG2 */
#define BIT_ANA_APB_USB30_CR_DATA_OUT(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_USB30_CR_DATA_IN(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_MIPI_PHY_CTRL1 */
#define BIT_ANA_APB_DSI_TXCLKESC_SEL				(BIT(31))
#define BIT_ANA_APB_DSI_REFCLK_SEL				(BIT(30))
#define BIT_ANA_APB_DSI_CFGCLK_SEL				(BIT(29))
#define BIT_ANA_APB_CSI_CFG_CLK_SEL				(BIT(28))
#define BIT_ANA_APB_DSI_PLLLOCK_S				(BIT(27))
#define BIT_ANA_APB_DSI_PLLLOCK_M				(BIT(26))
#define BIT_ANA_APB_CSI_IF_SEL					(BIT(25))
#define BIT_ANA_APB_DSI_IF_SEL					(BIT(24))
#define BIT_ANA_APB_CSI1_RX_RCTL(_X_)				((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_CSI0_RX_RCTL(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
#define BIT_ANA_APB_DSI_TRIMBG_S(_X_)				((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
#define BIT_ANA_APB_DSI_TX_RCTL_S(_X_)				((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
#define BIT_ANA_APB_DSI_TRIMBG_M(_X_)				((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
#define BIT_ANA_APB_DSI_TX_RCTL_M(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))

/* bits definitions for register REG_ANA_APB_MIPI_PHY_CTRL2 */
#define BIT_ANA_APB_CSI1_ENABLE_3				(BIT(31))
#define BIT_ANA_APB_CSI1_ENABLE_2				(BIT(30))
#define BIT_ANA_APB_CSI1_ENABLE_1				(BIT(29))
#define BIT_ANA_APB_CSI1_ENABLE_0				(BIT(28))
#define BIT_ANA_APB_CSI0_ENABLE_3				(BIT(27))
#define BIT_ANA_APB_CSI0_ENABLE_2				(BIT(26))
#define BIT_ANA_APB_CSI0_ENABLE_1				(BIT(25))
#define BIT_ANA_APB_CSI0_ENABLE_0				(BIT(24))
#define BIT_ANA_APB_DSI_ENABLE_3_S				(BIT(23))
#define BIT_ANA_APB_DSI_ENABLE_2_S				(BIT(22))
#define BIT_ANA_APB_DSI_ENABLE_1_S				(BIT(21))
#define BIT_ANA_APB_DSI_ENABLE_0_S				(BIT(20))
#define BIT_ANA_APB_DSI_ENABLE_3_M				(BIT(19))
#define BIT_ANA_APB_DSI_ENABLE_2_M				(BIT(18))
#define BIT_ANA_APB_DSI_ENABLE_1_M				(BIT(17))
#define BIT_ANA_APB_DSI_ENABLE_0_M				(BIT(16))
#define BIT_ANA_APB_DSI_BISTDONE_S				(BIT(15))
#define BIT_ANA_APB_DSI_BISTDONE_M				(BIT(14))
#define BIT_ANA_APB_CSI1_BISTOK					(BIT(13))
#define BIT_ANA_APB_CSI0_BISTOK					(BIT(12))
#define BIT_ANA_APB_CSI_BISTON					(BIT(11))
#define BIT_ANA_APB_CSI_ENABLECLK				(BIT(10))
#define BIT_ANA_APB_CSI_RSTZ					(BIT(9))
#define BIT_ANA_APB_CSI_SHUTDOWNZ				(BIT(8))
#define BIT_ANA_APB_DSI_TXREQUESTHSCLK_S			(BIT(7))
#define BIT_ANA_APB_DSI_TXREQUESTHSCLK_M			(BIT(6))
#define BIT_ANA_APB_DSI_FORCEPLL_S				(BIT(5))
#define BIT_ANA_APB_DSI_FORCEPLL_M				(BIT(4))
#define BIT_ANA_APB_DSI_BISTON					(BIT(3))
#define BIT_ANA_APB_DSI_ENABLECLK				(BIT(2))
#define BIT_ANA_APB_DSI_RSTZ					(BIT(1))
#define BIT_ANA_APB_DSI_SHUTDOWNZ				(BIT(0))

/* bits definitions for register REG_ANA_APB_MIPI_PHY_CTRL3 */
#define BIT_ANA_APB_DSI_TXREQUESTESC_3_S			(BIT(31))
#define BIT_ANA_APB_DSI_TXREQUESTESC_2_S			(BIT(30))
#define BIT_ANA_APB_DSI_TXREQUESTESC_1_S			(BIT(29))
#define BIT_ANA_APB_DSI_TXREQUESTESC_0_S			(BIT(28))
#define BIT_ANA_APB_DSI_TXREQUESTESC_3_M			(BIT(27))
#define BIT_ANA_APB_DSI_TXREQUESTESC_2_M			(BIT(26))
#define BIT_ANA_APB_DSI_TXREQUESTESC_1_M			(BIT(25))
#define BIT_ANA_APB_DSI_TXREQUESTESC_0_M			(BIT(24))
#define BIT_ANA_APB_DSI_TXDATAESC(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_DSI_TXVALIDESC_3_S				(BIT(15))
#define BIT_ANA_APB_DSI_TXVALIDESC_2_S				(BIT(14))
#define BIT_ANA_APB_DSI_TXVALIDESC_1_S				(BIT(13))
#define BIT_ANA_APB_DSI_TXVALIDESC_0_S				(BIT(12))
#define BIT_ANA_APB_DSI_TXVALIDESC_3_M				(BIT(11))
#define BIT_ANA_APB_DSI_TXVALIDESC_2_M				(BIT(10))
#define BIT_ANA_APB_DSI_TXVALIDESC_1_M				(BIT(9))
#define BIT_ANA_APB_DSI_TXVALIDESC_0_M				(BIT(8))
#define BIT_ANA_APB_DSI_TXLPDTESC_3_S				(BIT(7))
#define BIT_ANA_APB_DSI_TXLPDTESC_2_S				(BIT(6))
#define BIT_ANA_APB_DSI_TXLPDTESC_1_S				(BIT(5))
#define BIT_ANA_APB_DSI_TXLPDTESC_0_S				(BIT(4))
#define BIT_ANA_APB_DSI_TXLPDTESC_3_M				(BIT(3))
#define BIT_ANA_APB_DSI_TXLPDTESC_2_M				(BIT(2))
#define BIT_ANA_APB_DSI_TXLPDTESC_1_M				(BIT(1))
#define BIT_ANA_APB_DSI_TXLPDTESC_0_M				(BIT(0))

/* bits definitions for register REG_ANA_APB_MIPI_PHY_CTRL4 */
#define BIT_ANA_APB_DSI_STOPSTATEDATA_3_S			(BIT(31))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_2_S			(BIT(30))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_1_S			(BIT(29))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_0_S			(BIT(28))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_3_M			(BIT(27))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_2_M			(BIT(26))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_1_M			(BIT(25))
#define BIT_ANA_APB_DSI_STOPSTATEDATA_0_M			(BIT(24))
#define BIT_ANA_APB_CSI1_STOPSTATEDATA(_X_)			((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_CSI0_STOPSTATEDATA(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
#define BIT_ANA_APB_DSI_FORCERXMODE_3_S				(BIT(15))
#define BIT_ANA_APB_DSI_FORCERXMODE_2_S				(BIT(14))
#define BIT_ANA_APB_DSI_FORCERXMODE_1_S				(BIT(13))
#define BIT_ANA_APB_DSI_FORCERXMODE_0_S				(BIT(12))
#define BIT_ANA_APB_DSI_FORCERXMODE_3_M				(BIT(11))
#define BIT_ANA_APB_DSI_FORCERXMODE_2_M				(BIT(10))
#define BIT_ANA_APB_DSI_FORCERXMODE_1_M				(BIT(9))
#define BIT_ANA_APB_DSI_FORCERXMODE_0_M				(BIT(8))
#define BIT_ANA_APB_CSI1_FORCERXMODE_3				(BIT(7))
#define BIT_ANA_APB_CSI1_FORCERXMODE_2				(BIT(6))
#define BIT_ANA_APB_CSI1_FORCERXMODE_1				(BIT(5))
#define BIT_ANA_APB_CSI1_FORCERXMODE_0				(BIT(4))
#define BIT_ANA_APB_CSI0_FORCERXMODE_3				(BIT(3))
#define BIT_ANA_APB_CSI0_FORCERXMODE_2				(BIT(2))
#define BIT_ANA_APB_CSI0_FORCERXMODE_1				(BIT(1))
#define BIT_ANA_APB_CSI0_FORCERXMODE_0				(BIT(0))

/* bits definitions for register REG_ANA_APB_MPLL_CAL */
#define BIT_ANA_APB_MPLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_MPLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_RPLL_CAL */
#define BIT_ANA_APB_RPLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_RPLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_DPLL_CAL */
#define BIT_ANA_APB_DPLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_DPLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_TWPLL_CAL */
#define BIT_ANA_APB_TWPLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_TWPLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_LPLL_CAL */
#define BIT_ANA_APB_LPLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_LPLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_LVDS_PLL_CAL */
#define BIT_ANA_APB_LVDS_PLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_LVDS_PLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_DISP_PLL_CAL */
#define BIT_ANA_APB_DISP_PLL_MAX_RANGE(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)))
#define BIT_ANA_APB_DISP_PLL_MIN_RANGE(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))

/* bits definitions for register REG_ANA_APB_PLL_FREQ_CAL_CFG */
#define BIT_ANA_APB_DIV_NUM_26M(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)))
#define BIT_ANA_APB_DISP_PLL_CAL_SEL				(BIT(14))
#define BIT_ANA_APB_LVDS_PLL_CAL_SEL				(BIT(13))
#define BIT_ANA_APB_LPLL_CAL_SEL				(BIT(12))
#define BIT_ANA_APB_TWPLL_CAL_SEL				(BIT(11))
#define BIT_ANA_APB_DPLL_CAL_SEL				(BIT(10))
#define BIT_ANA_APB_RPLL_CAL_SEL				(BIT(9))
#define BIT_ANA_APB_MPLL_CAL_SEL				(BIT(8))
#define BIT_ANA_APB_DISP_PLL_CAL_EN				(BIT(6))
#define BIT_ANA_APB_LVDS_PLL_CAL_EN				(BIT(5))
#define BIT_ANA_APB_LPLL_CAL_EN					(BIT(4))
#define BIT_ANA_APB_TWPLL_CAL_EN				(BIT(3))
#define BIT_ANA_APB_DPLL_CAL_EN					(BIT(2))
#define BIT_ANA_APB_RPLL_CAL_EN					(BIT(1))
#define BIT_ANA_APB_MPLL_CAL_EN					(BIT(0))

/* bits definitions for register REG_ANA_APB_MPLL_RESULT */
#define BIT_ANA_APB_MPLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_MPLL_READY					(BIT(1))
#define BIT_ANA_APB_MPLL_PASS					(BIT(0))

/* bits definitions for register REG_ANA_APB_RPLL_RESULT */
#define BIT_ANA_APB_RPLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_RPLL_READY					(BIT(1))
#define BIT_ANA_APB_RPLL_PASS					(BIT(0))

/* bits definitions for register REG_ANA_APB_DPLL_RESULT */
#define BIT_ANA_APB_DPLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_DPLL_READY					(BIT(1))
#define BIT_ANA_APB_DPLL_PASS					(BIT(0))

/* bits definitions for register REG_ANA_APB_TWPLL_RESULT */
#define BIT_ANA_APB_TWPLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_TWPLL_READY					(BIT(1))
#define BIT_ANA_APB_TWPLL_PASS					(BIT(0))

/* bits definitions for register REG_ANA_APB_LPLL_RESULT */
#define BIT_ANA_APB_LPLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LPLL_READY					(BIT(1))
#define BIT_ANA_APB_LPLL_PASS					(BIT(0))

/* bits definitions for register REG_ANA_APB_LVDS_PLL_RESULT */
#define BIT_ANA_APB_LVDS_PLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_LVDS_PLL_READY				(BIT(1))
#define BIT_ANA_APB_LVDS_PLL_PASS				(BIT(0))

/* bits definitions for register REG_ANA_APB_DISP_PLL_RESULT */
#define BIT_ANA_APB_DISP_PLL_FREQ(_X_)				((_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)))
#define BIT_ANA_APB_DISP_PLL_READY				(BIT(1))
#define BIT_ANA_APB_DISP_PLL_PASS				(BIT(0))

/* bits definitions for register REG_ANA_APB_PLL_TEST_FLAG */
#define BIT_ANA_APB_PLLS_FLAG(_X_)				(_X_)

/* bits definitions for register REG_ANA_APB_MIPI_TEST */
#define BIT_ANA_APB_MIPI_TESTDOUT_SEL				(BIT(31))
#define BIT_ANA_APB_MIPI1_TESTIN_SEL				(BIT(30))
#define BIT_ANA_APB_MIPI1_TESTEN				(BIT(29))
#define BIT_ANA_APB_MIPI1_TESTCLR				(BIT(28))
#define BIT_ANA_APB_MIPI1_TESTCLK				(BIT(27))
#define BIT_ANA_APB_MIPI0_TESTEN				(BIT(26))
#define BIT_ANA_APB_MIPI0_TESTCLR				(BIT(25))
#define BIT_ANA_APB_MIPI0_TESTCLK				(BIT(24))
#define BIT_ANA_APB_MIPI_TEST_IF_SEL				(BIT(23))
#define BIT_ANA_APB_MIPI_TEST_DONE				(BIT(22))
#define BIT_ANA_APB_MIPI_TEST_PASS				(BIT(21))
#define BIT_ANA_APB_MIPI_TEST_DA_LEN(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)))
#define BIT_ANA_APB_MIPI_TEST_DLAN_SEL(_X_)			((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)))
#define BIT_ANA_APB_MIPI_TEST_CLAN_SEL(_X_)			((_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)))
#define BIT_ANA_APB_MIPI_TEST_EN				(BIT(0))

/* bits definitions for register REG_ANA_APB_MIPI_TEST2 */
#define BIT_ANA_APB_MIPI1_TESTDOUT(_X_)			((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_MIPI1_TESTDIN(_X_)				((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
#define BIT_ANA_APB_MIPI0_TESTDOUT(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
#define BIT_ANA_APB_MIPI0_TESTDIN(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))

/* bits definitions for register REG_ANA_APB_MIPI_CSI0_RESERVE */
#define BIT_ANA_APB_CSI0_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_MIPI_CSI1_RESERVE */
#define BIT_ANA_APB_CSI1_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_MIPI_DSI0_RESERVE */
#define BIT_ANA_APB_DSI0_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_MIPI_DSI1_RESERVE */
#define BIT_ANA_APB_DSI1_RESERVE(_X_)				((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_LVDSDISP_BIST_CFG1 */
#define BIT_ANA_APB_DISP_DC_TX_SEL(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)))
#define BIT_ANA_APB_DISP_BIST_TX_SEL(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))
#define BIT_ANA_APB_DISP_BIST_RX_FAIL				(BIT(7))
#define BIT_ANA_APB_DISP_BIST_RX_FAIL_STS			(BIT(6))
#define BIT_ANA_APB_DISP_BIST_RX_SYNC_DET			(BIT(5))
#define BIT_ANA_APB_DISP_BIST_RX_PHALIGN_LOCK_DONE		(BIT(4))
#define BIT_ANA_APB_DISP_BIST_RX_EN				(BIT(3))
#define BIT_ANA_APB_DISP_BIST_TX_EN				(BIT(2))
#define BIT_ANA_APB_DISP_BIST_RX_PHALIGN_EN			(BIT(1))
#define BIT_ANA_APB_DISP_BIST_TX_PHALIGN_EN			(BIT(0))

/* bits definitions for register REG_ANA_APB_LVDSDISP_BIST_CFG2 */
#define BIT_ANA_APB_DISP_DC_TX_DATA1(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_DISP_DC_TX_DATA0(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_DISP_DC_TX_CLKDATA(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)))

/* bits definitions for register REG_ANA_APB_LVDSDISP_BIST_CFG3 */
#define BIT_ANA_APB_DISP_DC_TX_DATA4(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)))
#define BIT_ANA_APB_DISP_DC_TX_DATA3(_X_)			((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)))
#define BIT_ANA_APB_DISP_DC_TX_DATA2(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)))

/* bits definitions for register REG_ANA_APB_MACRO_POWER_FLAG0 */
#define BIT_ANA_APB_MACRO_POWER_FLAG0(_X_)			(_X_)

/* bits definitions for register REG_ANA_APB_MACRO_POWER_FLAG1 */
#define BIT_ANA_APB_MACRO_POWER_FLAG1(_X_)			(_X_)

/* bits definitions for register REG_ANA_APB_MACRO_RESET_FLAG0 */
#define BIT_ANA_APB_MACRO_RESET_FLAG0(_X_)			(_X_)

/* bits definitions for register REG_ANA_APB_MACRO_CHECK_FLAG0 */
#define BIT_ANA_APB_MACRO_CHECK_FLAG0(_X_)			(_X_)

/* bits definitions for register REG_ANA_APB_MACRO_CHECK_FLAG1 */
#define BIT_ANA_APB_MACRO_CHECK_FLAG1(_X_)			(_X_)

/* bits definitions for register REG_ANA_APB_PLL_CLKOUT_AUTO_GATE0 */
#define BIT_ANA_APB_GPLL_CLKOUT_AUTO_GATE_DIS			(BIT(27))
#define BIT_ANA_APB_LPLL0_CLKOUT_AUTO_GATE_DIS			(BIT(26))
#define BIT_ANA_APB_LPLL0_DIV1_AUTO_GATE_DIS			(BIT(25))
#define BIT_ANA_APB_LPLL0_DIV2_AUTO_GATE_DIS			(BIT(24))
#define BIT_ANA_APB_LPLL0_DIV3_AUTO_GATE_DIS			(BIT(23))
#define BIT_ANA_APB_LPLL0_DIV5_AUTO_GATE_DIS			(BIT(22))
#define BIT_ANA_APB_TWPLL_CLKOUT_AUTO_GATE_DIS			(BIT(21))
#define BIT_ANA_APB_TWPLL_DIV1_AUTO_GATE_DIS			(BIT(20))
#define BIT_ANA_APB_TWPLL_DIV2_AUTO_GATE_DIS			(BIT(19))
#define BIT_ANA_APB_TWPLL_DIV3_AUTO_GATE_DIS			(BIT(18))
#define BIT_ANA_APB_TWPLL_DIV5_AUTO_GATE_DIS			(BIT(17))
#define BIT_ANA_APB_TWPLL_DIV7_AUTO_GATE_DIS			(BIT(16))
#define BIT_ANA_APB_DPLL1_CLKOUT_AUTO_GATE_DIS			(BIT(15))
#define BIT_ANA_APB_DPLL1_DIV1_AUTO_GATE_DIS			(BIT(14))
#define BIT_ANA_APB_DPLL1_DIV2_AUTO_GATE_DIS			(BIT(13))
#define BIT_ANA_APB_DPLL1_DIV3_AUTO_GATE_DIS			(BIT(12))
#define BIT_ANA_APB_DPLL1_DIV4_AUTO_GATE_DIS			(BIT(11))
#define BIT_ANA_APB_DPLL1_DIV5_AUTO_GATE_DIS			(BIT(10))
#define BIT_ANA_APB_DPLL1_DIV7_AUTO_GATE_DIS			(BIT(9))
#define BIT_ANA_APB_DPLL0_CLKOUT_AUTO_GATE_DIS			(BIT(8))
#define BIT_ANA_APB_DPLL0_DIV1_AUTO_GATE_DIS			(BIT(7))
#define BIT_ANA_APB_DPLL0_DIV2_AUTO_GATE_DIS			(BIT(6))
#define BIT_ANA_APB_DPLL0_DIV3_AUTO_GATE_DIS			(BIT(5))
#define BIT_ANA_APB_DPLL0_DIV4_AUTO_GATE_DIS			(BIT(4))
#define BIT_ANA_APB_DPLL0_DIV5_AUTO_GATE_DIS			(BIT(3))
#define BIT_ANA_APB_DPLL0_DIV7_AUTO_GATE_DIS			(BIT(2))
#define BIT_ANA_APB_MPLL1_CLKOUT_AUTO_GATE_DIS			(BIT(1))
#define BIT_ANA_APB_MPLL0_CLKOUT_AUTO_GATE_DIS			(BIT(0))

/* bits definitions for register REG_ANA_APB_PLL_CLKOUT_AUTO_GATE1 */
#define BIT_ANA_APB_LPLL1_CLKOUT_AUTO_GATE_DIS			(BIT(4))
#define BIT_ANA_APB_LPLL1_DIV1_AUTO_GATE_DIS			(BIT(3))
#define BIT_ANA_APB_LPLL1_DIV2_AUTO_GATE_DIS			(BIT(2))
#define BIT_ANA_APB_LPLL1_DIV3_AUTO_GATE_DIS			(BIT(1))
#define BIT_ANA_APB_LPLL1_DIV5_AUTO_GATE_DIS			(BIT(0))

/* bits definitions for register REG_ANA_APB_AGLB_SEL0 */
#define BIT_ANA_APB_USB30_CFG_SEL				(BIT(25))
#define BIT_ANA_APB_HSIC_CFG_SEL				(BIT(24))
#define BIT_ANA_APB_USB20_CFG_SEL				(BIT(23))
#define BIT_ANA_APB_MIPI_CSI_CFG_SEL				(BIT(22))
#define BIT_ANA_APB_MIPI_DSI_CFG_SEL				(BIT(21))
#define BIT_ANA_APB_LVDSDIS_CFG_SEL				(BIT(20))
#define BIT_ANA_APB_S_LVDSRF_CFG_SEL				(BIT(19))
#define BIT_ANA_APB_M_LVDSRF_CFG_SEL				(BIT(18))
#define BIT_ANA_APB_THM_CFG_SEL					(BIT(17))
#define BIT_ANA_APB_GPLL_CFG_SEL				(BIT(16))
#define BIT_ANA_APB_DISP_PLL_CFG_SEL				(BIT(15))
#define BIT_ANA_APB_TWPLL_CFG_SEL				(BIT(14))
#define BIT_ANA_APB_S_LVDSRF_PLL_CFG_SEL			(BIT(13))
#define BIT_ANA_APB_M_LVDSRF_PLL_CFG_SEL			(BIT(12))
#define BIT_ANA_APB_LPLL1_CFG_SEL				(BIT(11))
#define BIT_ANA_APB_LPLL0_CFG_SEL				(BIT(10))
#define BIT_ANA_APB_RPLL1_CFG_SEL				(BIT(9))
#define BIT_ANA_APB_RPLL0_CFG_SEL				(BIT(8))
#define BIT_ANA_APB_DPLL1_CFG_SEL				(BIT(7))
#define BIT_ANA_APB_DPLL0_CFG_SEL				(BIT(6))
#define BIT_ANA_APB_MPLL1_CFG_SEL				(BIT(5))
#define BIT_ANA_APB_MPLL0_CFG_SEL				(BIT(4))
#define BIT_ANA_APB_RTC_CFG_SEL					(BIT(3))
#define BIT_ANA_APB_AAPC_CFG_SEL				(BIT(2))
#define BIT_ANA_APB_BB_BG_CFG_SEL				(BIT(1))
#define BIT_ANA_APB_XTAL_SIN_CFG_SEL				(BIT(0))

/* bits definitions for register REG_ANA_APB_AGLB_SEL1 */
#define BIT_ANA_APB_PLL_ATE_REFCK_SEL				(BIT(7))
#define BIT_ANA_APB_MIPI_ATE_REFCK_SEL				(BIT(6))
#define BIT_ANA_APB_MDAR_PMU_RPLL1_CFG_SEL			(BIT(5))
#define BIT_ANA_APB_MDAR_PMU_RPLL0_CFG_SEL			(BIT(4))
#define BIT_ANA_APB_ANLG_DBG_BUS_SEL(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))

/* bits definitions for register REG_ANA_APB_SW_TEST */
#define BIT_ANA_APB_SW_FLAG					(BIT(0))

/* bits definitions for register REG_ANA_APB_ANLG_RESERVED1 */
#define BIT_ANA_APB_ANLG_RESERVED1_HB(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_ANLG_RESERVED1_LB(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

/* bits definitions for register REG_ANA_APB_ANLG_RESERVED2 */
#define BIT_ANA_APB_ANLG_RESERVED2_HB(_X_)			((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
#define BIT_ANA_APB_ANLG_RESERVED2_LB(_X_)			((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))

#endif
